29 lines
514 B
Systemverilog
29 lines
514 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [31:0] a, b;
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integer cyc = 0;
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assign a = 'z;
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alias a = b;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (a !== 'z) $stop;
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if (b !== 'z) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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