35 lines
718 B
Systemverilog
35 lines
718 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [15:0] a, b;
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integer cyc = 0;
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alias a = b;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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force a = 16'h1234;
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if (a != 16'h1234 || a != b) $stop;
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release a;
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end else if (cyc == 2) begin
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force b = 16'h5678;
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if (a != 16'h5678 || a != b) $stop;
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release b;
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end else if (cyc == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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