32 lines
642 B
Systemverilog
32 lines
642 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional transitive alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [31:0] a = 32'hdeadbeef;
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wire [31:0] b;
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alias a = a;
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alias a = b;
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alias b = a;
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("a = %x, b = %x\n", a, b);
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`endif
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if (b != 32'hdeadbeef) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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