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verilator/test_regress
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Geza Lore 59cb53cfbc Set trigger vector in whole words (#5857) 
Having many triggers still hits a bottleneck in LLVM leading to long
compile times.

Instead of setting triggers bit-wise, set them as a whole 64-bit word
when possible. This improves C++ compile times by ~4x on some large
designs and has minor run-time performance benefit.
2025-03-14 14:06:51 +00:00
..
t
Set trigger vector in whole words (#5857)
2025-03-14 14:06:51 +00:00
.gdbinit
Revert .gdbinit modified by accident. (#4330)
2023-06-30 16:57:31 -04:00
.gitignore
…
CMakeLists.txt
Copyright year update.
2025-01-01 08:30:25 -05:00
driver.py
Add --trace-saif for SAIF power traces (#5812)
2025-03-07 10:41:29 -05:00
input.vc
Tests: Avoid verilated.v include in most tests
2024-02-27 18:08:37 -05:00
input.xsim.vc
Tests: Avoid verilated.v include in most tests
2024-02-27 18:08:37 -05:00
Makefile
Copyright year update.
2025-01-01 08:30:25 -05:00
Makefile_obj
Copyright year update.
2025-01-01 08:30:25 -05:00