39 lines
907 B
Systemverilog
39 lines
907 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top_module(
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input reg [7:0] in1a,
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input reg [7:0] in2a,
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input reg [7:0] in1b,
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input reg [7:0] in2b,
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output logic [7:0] outa,
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output logic [7:0] outb
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);
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module_a a1 (.in1(in1a), .in2(in2a), .out(outa));
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module_a a2 (.in1(in1b), .in2(in2b), .out(outb));
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endmodule
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module module_a(
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input logic [7:0] in1,
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input logic [7:0] in2,
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output logic [7:0] out
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);
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module_b b1 (.in1(in1), .in2(in2), .out(out));
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endmodule
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module module_b (
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input logic [7:0] in1,
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input logic [7:0] in2,
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output logic [7:0] out
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);
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reg [127:0] bigRegister;
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always_comb begin
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out = in1 + in2;
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end
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endmodule
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