74 lines
1.6 KiB
Systemverilog
74 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int unsigned crc = 32'h1;
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bit a, b, rst;
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bit a1;
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int cyc;
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int hits, ref_hits, one_hits, one_ref;
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// Neither the default disable iff nor $assertoff may suppress a sequence event control
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default disable iff (rst);
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// verilog_format: off // verible does not support clocking events inside sequence declarations
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sequence seq;
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@(posedge clk) a ##1 b;
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endsequence
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sequence seq_one;
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@(posedge clk) 1;
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endsequence
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// verilog_format: on
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initial begin
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$assertoff;
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#300 $assertkill;
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end
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initial forever begin
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@seq;
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hits = hits + 1;
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end
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initial forever begin
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@seq_one;
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one_hits = one_hits + 1;
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end
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always @(posedge clk) begin
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if (a1 && b) ref_hits = ref_hits + 1;
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one_ref = one_ref + 1;
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a1 <= a;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[30:0], crc[31] ^ crc[21] ^ crc[1] ^ crc[0]};
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a <= crc[0];
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b <= crc[4];
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rst <= crc[2];
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end
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always @(negedge clk) begin
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if (cyc == 60) $finish;
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end
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final begin
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`checkd(hits, ref_hits);
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`checkd(one_hits, one_ref);
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`checkd(hits, 19);
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`checkd(one_hits, 60);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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