98 lines
2.3 KiB
Systemverilog
98 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int unsigned crc = 32'h1;
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bit a, b, c;
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bit a1, a2, a3, b1;
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int cyc;
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int seq_hits, seq_hits2, ref_hits, one_hits, dc_hits;
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int rng_hits, rng_ref;
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// verilog_format: off // verible does not support clocking events inside sequence declarations
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sequence seq;
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@(posedge clk) a ##1 b ##1 c;
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endsequence
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sequence seq_one;
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@(posedge clk) a;
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endsequence
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sequence seq_rng;
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@(posedge clk) a ##[1:3] b;
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endsequence
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// verilog_format: on
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// seq_dc inherits the default clocking; counts must match seq
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default clocking @(posedge clk);
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endclocking
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sequence seq_dc;
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a ##1 b ##1 c;
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endsequence
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// ref_hits and rng_ref are independent shift-register oracles;
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// simultaneous end points resume a blocked waiter once
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initial forever begin
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@seq;
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seq_hits = seq_hits + 1;
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end
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initial forever begin
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@seq;
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seq_hits2 = seq_hits2 + 1;
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end
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initial forever begin
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@seq_one;
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one_hits = one_hits + 1;
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end
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initial forever begin
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@seq_dc;
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dc_hits = dc_hits + 1;
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end
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initial forever begin
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@seq_rng;
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rng_hits = rng_hits + 1;
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end
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always @(posedge clk) begin
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if (a2 && b1 && c) ref_hits = ref_hits + 1;
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if (b && (a1 || a2 || a3)) rng_ref = rng_ref + 1;
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a3 <= a2;
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a2 <= a1;
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a1 <= a;
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b1 <= b;
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end
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// a/b/c bit spacing exceeds the ##2 window to decorrelate the LFSR taps
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[30:0], crc[31] ^ crc[21] ^ crc[1] ^ crc[0]};
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a <= crc[0];
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b <= crc[4];
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c <= crc[8];
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if (cyc == 60) $finish;
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end
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// Counts read in final (Postponed) to avoid same-timestep races.
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final begin
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`checkd(seq_hits, 14);
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`checkd(seq_hits2, 14);
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`checkd(ref_hits, 14);
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`checkd(one_hits, 30);
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`checkd(dc_hits, 14);
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`checkd(rng_hits, 26);
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`checkd(rng_ref, 26);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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