318 lines
12 KiB
Systemverilog
318 lines
12 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA.
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// If split_var pragma is removed, UNOPTFLAT appears.
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module barshift_1d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = -3;
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logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
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end
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else begin
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tmp[i+1+OFFSET] = tmp[i+OFFSET];
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end
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end
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endgenerate
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assign tmp[0+OFFSET] = in;
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assign out = tmp[DEPTH+OFFSET];
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endmodule
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module barshift_1d_unpacked_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = -3;
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// almost same as above module, but tmp[smaller:bigger] here.
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logic [WIDTH-1:0] tmp[OFFSET:DEPTH+OFFSET]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
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end
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else begin
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tmp[i+1+OFFSET] = tmp[i+OFFSET];
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end
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end
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endgenerate
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assign tmp[0+OFFSET] = in;
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assign out = tmp[DEPTH+OFFSET];
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endmodule
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module barshift_1d_unpacked_struct0 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = 1;
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typedef struct packed { logic [WIDTH-1:0] data; } data_type;
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data_type tmp[DEPTH+OFFSET:OFFSET]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
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end
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else begin
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tmp[i+1+OFFSET] = tmp[i+OFFSET];
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end
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end
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endgenerate
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assign tmp[0+OFFSET] = in;
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assign out = tmp[DEPTH+OFFSET];
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endmodule
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module barshift_2d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = 1;
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localparam N = 3;
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reg [WIDTH-1:0] tmp0[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp1[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp2[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1];
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reg [WIDTH-1:0] tmp3[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp4[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp5[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1];
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reg [WIDTH-1:0] tmp6[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp7[DEPTH+OFFSET+1:OFFSET+1][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp8[DEPTH+OFFSET+3:OFFSET-1][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp9[DEPTH+OFFSET+3:OFFSET+3][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp10[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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// because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar,
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// UNOPTFLAT appears, but it's fine.
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/*verilator lint_off UNOPTFLAT*/
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reg [WIDTH-1:0] tmp11[-1:1][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1];
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/*verilator lint_on UNOPTFLAT*/
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reg [WIDTH-1:0] tmp12[-1:0][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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reg [WIDTH-1:0] tmp13[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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for(genvar j = OFFSET; j < N + OFFSET; ++j) begin
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always_comb
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if (shift[i]) begin
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tmp0[i+1+OFFSET][j] = {tmp0[i+OFFSET][j][(1 << i)-1:0], tmp0[i+OFFSET][j][WIDTH-1:(2**i)]};
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end
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else begin
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tmp0[i+1+OFFSET][j] = tmp0[i+OFFSET][j];
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end
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end
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end
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for(genvar j = OFFSET; j < N + OFFSET; ++j) begin
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assign tmp0[0 + OFFSET][j] = in;
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end
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endgenerate
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assign tmp1 = tmp0; // split both side
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assign tmp2 = tmp1; // split only rhs
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assign tmp3 = tmp2; // split only lhs
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always_comb tmp4 = tmp3; // split both side
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always_comb tmp5 = tmp4; // split only rhs
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always_comb tmp6 = tmp5; // split only lhs
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assign tmp7 = tmp6;
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assign tmp8[DEPTH+OFFSET+1:OFFSET+1] = tmp7;
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assign tmp9 = tmp8[DEPTH+OFFSET+1:OFFSET+1];
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assign tmp10[DEPTH+OFFSET:OFFSET] = tmp9[DEPTH+OFFSET+3:OFFSET+3];
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assign tmp11[1] = tmp10;
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assign tmp11[-1] = tmp11[1];
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assign tmp11[0] = tmp11[-1];
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assign tmp12 = tmp11[0:1];
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assign out = tmp12[1][DEPTH+OFFSET][OFFSET];
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endmodule
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module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = 2;
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typedef struct packed { int data; } data_type;
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data_type tmp[DEPTH+OFFSET:OFFSET]; /*verilator split_var*/
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localparam [32-WIDTH-1:0] pad = 0;
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+OFFSET] = {pad, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
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end
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else begin
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tmp[i+1+OFFSET] = tmp[i+OFFSET];
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end
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end
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endgenerate
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assign tmp[0+OFFSET] = {pad, in};
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assign out = tmp[DEPTH+OFFSET][WIDTH-1:0];
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endmodule
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module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = -2;
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/*verilator lint_off LITENDIAN*/
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reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp; /*verilator split_var*/
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/*verilator lint_on LITENDIAN*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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/*verilator lint_off ALWCOMBORDER*/
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if (shift[i]) begin
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tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
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end
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else begin
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tmp[i+1+OFFSET][1:0] = tmp[i+OFFSET][1:0];
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tmp[i+1+OFFSET][WIDTH-1:2] = tmp[i+OFFSET][WIDTH-1:2];
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end
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/*verilator lint_on ALWCOMBORDER*/
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end
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endgenerate
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assign tmp[0+OFFSET] = in;
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assign out = tmp[DEPTH+OFFSET];
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endmodule
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module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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localparam OFFSET = -2;
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/*verilator lint_off LITENDIAN*/
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reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp; /*verilator split_var*/
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/*verilator lint_on LITENDIAN*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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/*verilator lint_off ALWCOMBORDER*/
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if (shift[i]) begin
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tmp[i+1+OFFSET] = {tmp[i+OFFSET][WIDTH-(2**i)+OFFSET:WIDTH-1+OFFSET], tmp[i+OFFSET][OFFSET:WIDTH-(2**i)-1+OFFSET]};
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end
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else begin // actulally just tmp[i+1+OFFSET] = tmp[i+OFFSET]
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tmp[i+1+OFFSET][0+OFFSET:2+OFFSET] = tmp[i+OFFSET][0+OFFSET:2+OFFSET];
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tmp[i+1+OFFSET][3+OFFSET] = tmp[i+OFFSET][3+OFFSET];
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{tmp[i+1+OFFSET][4+OFFSET],tmp[i+1+OFFSET][5+OFFSET]} = {tmp[i+OFFSET][4+OFFSET], tmp[i+OFFSET][5+OFFSET]};
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{tmp[i+1+OFFSET][7+OFFSET],tmp[i+1+OFFSET][6+OFFSET]} = {tmp[i+OFFSET][7+OFFSET], tmp[i+OFFSET][6+OFFSET]};
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end
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/*verilator lint_on ALWCOMBORDER*/
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end
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endgenerate
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assign tmp[0+OFFSET] = in;
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assign out = tmp[DEPTH+OFFSET];
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endmodule
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module barshift_1d_packed_struct #(localparam DEPTH = 3, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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typedef struct packed {
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logic [WIDTH-1:0] v0, v1, v2, v3;
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} data_type;
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wire data_type tmp; /*verilator split_var*/
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assign tmp.v0 = in;
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assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[WIDTH-1:2**0]} : tmp.v0;
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assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[WIDTH-1:2**1]} : tmp.v1;
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assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[WIDTH-1:2**2]} : tmp.v2;
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assign out = tmp.v3;
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endmodule
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module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
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(input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
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/*verilator lint_off LITENDIAN*/
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wire [0:WIDTH*(DEPTH+1) - 1] tmp; /*verilator split_var*/
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/*verilator lint_on LITENDIAN*/
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generate
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for(genvar i = 0; i < DEPTH; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = {tmp[WIDTH*(i+1)-(1<<i):WIDTH*(i+1)-1], tmp[WIDTH*i:WIDTH*i+((WIDTH-1) - (2**i))]};
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end
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else begin
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tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = tmp[WIDTH*i:WIDTH*(i+1)-1];
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end
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end
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endgenerate
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assign tmp[WIDTH*0:WIDTH*(0+1)-1] = in;
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assign out = tmp[WIDTH*DEPTH:WIDTH*(DEPTH+1)-1];
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endmodule
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module var_decl_with_init();
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/*verilator lint_off LITENDIAN*/
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logic [-1:30] var0 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */
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logic [-1:30] var2; /* verilator split_var */
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/*verilator lint_on LITENDIAN*/
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logic [30:-1] var1 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */
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logic [30:-1] var3; /* verilator split_var */
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initial begin
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var2[-1:2] = 4'd2;
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var3[2:-1] = 4'd3;
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$display("%x %x", var0, var1);
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$display("%x %x", var2, var3);
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var0[-1:5] = 7'd0;
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var1[10:3] = 8'd2;
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end
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endmodule
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module t(/*AUTOARG*/ clk);
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input clk;
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localparam DEPTH = 3;
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localparam WIDTH = 2**DEPTH;
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localparam NUMSUB = 9;
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logic [WIDTH-1:0] in;
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logic [WIDTH-1:0] out[0:NUMSUB-1];
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logic [DEPTH-1:0] shift = 0;
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// barrel shifter
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barshift_1d_unpacked #(.DEPTH(DEPTH)) shifter0(.in(in), .out(out[0]), .shift(shift));
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barshift_1d_unpacked_le #(.DEPTH(DEPTH)) shifter1(.in(in), .out(out[1]), .shift(shift));
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barshift_1d_unpacked_struct0 #(.DEPTH(DEPTH)) shifter2(.in(in), .out(out[2]), .shift(shift));
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barshift_2d_unpacked #(.DEPTH(DEPTH)) shifter3(.in(in), .out(out[3]), .shift(shift));
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barshift_1d_unpacked_struct1 #(.DEPTH(DEPTH)) shifter4(.in(in), .out(out[4]), .shift(shift));
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barshift_2d_packed_array #(.DEPTH(DEPTH)) shifter5(.in(in), .out(out[5]), .shift(shift));
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barshift_2d_packed_array_le #(.DEPTH(DEPTH)) shifter6(.in(in), .out(out[6]), .shift(shift));
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barshift_1d_packed_struct shifter7(.in(in), .out(out[7]), .shift(shift));
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barshift_bitslice #(.DEPTH(DEPTH)) shifter8(.in(in), .out(out[8]), .shift(shift));
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var_decl_with_init i_var_decl_with_init();
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assign in = 8'b10001110;
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/*verilator lint_off LITENDIAN*/
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logic [7:0] [7:0] expc
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= {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
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8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
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/*verilator lint_on LITENDIAN*/
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always @(posedge clk) begin : always_block
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automatic bit failed = 0;
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$display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]);
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for (int i = 0; i < NUMSUB; ++i) begin
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if (out[i] != expc[7-shift]) begin
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$display("Missmatch out[%d]:%b", i, out[i]);
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failed = 1;
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end
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end
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if (failed) $stop;
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if (shift == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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shift <= shift + 1;
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end
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endmodule
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