Geza Lore a966e6aa13 Improve automatic selection of logic for Dfg synthesis (#6370) ... Reduce set of synthesized logic to be more in-line with what Dfg used to handle before + drivers of circular variables. This was always the intention but the previous algorithm was both a bit too eager, and also missed some circular variables. We can add back more heuristics based on performance measurements for non-circular logic later.		2025-09-05 08:14:48 +01:00
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t	Improve automatic selection of logic for Dfg synthesis (#6370)	2025-09-05 08:14:48 +01:00
.gdbinit	…
.gitignore	…
CMakeLists.txt	Copyright year update.	2025-01-01 08:30:25 -05:00
Makefile	Adjust make test-snap / make test-diff rules	2025-08-05 14:41:38 +01:00
Makefile_obj	Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk.	2025-07-28 18:01:50 -04:00
driver.py	Improve testing on FreeBSD (#6328)	2025-08-23 10:49:03 -04:00
input.vc	…
input.xsim.vc	…