34 lines
903 B
Systemverilog
34 lines
903 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class Cls;
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task test_srandom;
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int i, j, k;
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// $urandom is per-process thread, not affected by object stability/this.srandom(seed)
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// "Each object maintains its own internal RNG, which is used exclusively by its randomize() method."
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// THis was moved to t_rand_stability_class.v
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this.srandom(1234);
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i = $urandom;
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this.srandom(1234);
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j = $urandom;
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this.srandom(1234);
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k = $urandom;
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if (i == j && i == k) $stop; // Small chance randomly i == j, or j == k
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endtask
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endclass
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Cls c1;
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initial begin
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c1 = new;
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c1.test_srandom;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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