48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Sergey Chusov
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// SPDX-License-Identifier: CC0-1.0
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// A factory-like static method, as used by UVM's type_id::create().
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class registry #(type T = int);
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static function T create();
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T r = new;
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return r;
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endfunction
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endclass
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class item;
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int val;
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typedef registry#(item) type_id;
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function new();
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val = 42;
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endfunction
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endclass
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class seq_base #(type REQ = int, type RSP = REQ);
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REQ req;
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endclass
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// Non-parameterized class extending a parameterized base.
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// REQ is a type parameter inherited from the (specialized) base class and is
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// here used as a '::' class scope: REQ::type_id::create(). Resolving REQ in
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// this position requires deferring until after V3Param has bound REQ to item.
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class seq extends seq_base #(item);
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function int make();
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REQ r;
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r = REQ::type_id::create();
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return r.val;
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endfunction
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endclass
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module t;
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seq s;
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initial begin
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s = new;
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if (s.make() != 42) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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