verilator/test_regress
Varun Koyyalagunta a3003a2d0f
Add 15 new DFG peephole optimizations (#7553)
- FOLD_SELF_SUB: x - x -> 0
- REMOVE_DIV_ONE / REMOVE_DIVS_ONE: x / 1 -> x (unsigned and signed)
- REMOVE_MUL_ZERO / REMOVE_MUL_ONE / REMOVE_MULS_ZERO / REMOVE_MULS_ONE:
  0 * x -> 0 and 1 * x -> x (unsigned and signed)
- REPLACE_NOT_LT/GTE/GT/LTE and their signed counterparts: eliminate a
  Not vertex by flipping the comparison operator

Test signals for the NOT-of-comparison GT/GTE variants use unique shift
amounts to prevent intra-pass CSE from merging their DfgGt/DfgGte vertices
with those produced when the complementary LT/LTE patterns fire, which
would otherwise trigger the !hasMultipleSinks() guard.
2026-05-08 12:39:33 -05:00
..
t Add 15 new DFG peephole optimizations (#7553) 2026-05-08 12:39:33 -05:00
.gdbinit
.gitignore
CMakeLists.txt Remove multi-threaded FST tracing (#7443) 2026-04-19 16:02:12 +01:00
Makefile Test: Remove old Makefile rules 2026-04-13 21:09:09 -04:00
Makefile_obj Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
driver.py Tests: Make xrun fail on stop (#7547) 2026-05-08 07:39:38 -04:00
input.vc
input.xsim.vc