63 lines
3.1 KiB
XML
63 lines
3.1 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2023"/>
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<file id="b" filename="<command-line>" language="1800-2023"/>
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<file id="c" filename="input.vc" language="1800-2023"/>
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<file id="d" filename="t/t_xml_primary_io.v" language="1800-2023"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_xml_primary_io.v" language="1800-2023"/>
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</module_files>
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<cells>
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<cell loc="d,7,8,7,11" name="top" submodname="top" hier="top">
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<cell loc="d,15,11,15,19" name="and_cell" submodname="and2_x1" hier="top.and_cell"/>
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</cell>
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</cells>
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<netlist>
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<module loc="d,7,8,7,11" name="top" origName="top" topModule="1">
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<var loc="d,8,9,8,12" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk" public="true"/>
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<var loc="d,9,9,9,11" name="a1" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="a1" public="true"/>
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<var loc="d,10,9,10,11" name="a2" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="a2" public="true"/>
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<var loc="d,11,10,11,15" name="ready" dtype_id="1" dir="output" pinIndex="4" vartype="logic" origName="ready" public="true"/>
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<var loc="d,13,8,13,17" name="ready_reg" dtype_id="1" vartype="logic" origName="ready_reg"/>
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<instance loc="d,15,11,15,19" name="and_cell" defName="and2_x1" origName="and_cell">
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<port loc="d,16,6,16,8" name="a1" direction="in" portIndex="1">
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<varref loc="d,16,9,16,11" name="a1" dtype_id="1"/>
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</port>
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<port loc="d,17,6,17,8" name="a2" direction="in" portIndex="2">
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<varref loc="d,17,9,17,11" name="a2" dtype_id="1"/>
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</port>
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<port loc="d,18,6,18,8" name="zn" direction="out" portIndex="3">
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<varref loc="d,18,9,18,18" name="ready_reg" dtype_id="1"/>
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</port>
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</instance>
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<always loc="d,21,16,21,17">
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<contassign loc="d,21,16,21,17" dtype_id="1">
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<varref loc="d,13,8,13,17" name="ready_reg" dtype_id="1"/>
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<varref loc="d,21,16,21,17" name="ready" dtype_id="1"/>
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</contassign>
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</always>
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</module>
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<module loc="d,24,8,24,15" name="and2_x1" origName="and2_x1">
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<var loc="d,25,14,25,16" name="a1" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="a1"/>
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<var loc="d,26,14,26,16" name="a2" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="a2"/>
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<var loc="d,27,15,27,17" name="zn" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="zn"/>
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<always loc="d,29,15,29,16">
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<contassign loc="d,29,15,29,16" dtype_id="1">
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<and loc="d,29,21,29,22" dtype_id="1">
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<varref loc="d,25,14,25,16" name="a1" dtype_id="1"/>
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<varref loc="d,26,14,26,16" name="a2" dtype_id="1"/>
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</and>
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<varref loc="d,29,15,29,16" name="zn" dtype_id="1"/>
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</contassign>
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</always>
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</module>
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<typetable loc="a,0,0,0,0">
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<basicdtype loc="d,25,14,25,16" id="1" name="logic"/>
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<voiddtype loc="a,0,0,0,0" id="2"/>
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</typetable>
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</netlist>
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</verilator_xml>
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