24 lines
1.6 KiB
Plaintext
24 lines
1.6 KiB
Plaintext
%Warning-MODDUP: t/t_sarif.v:20:8: Duplicate declaration of module: 't'
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20 | module t;
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| ^
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t/t_sarif.v:7:8: ... Location of original declaration
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7 | module t (
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| ^
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... For warning description see https://verilator.org/warn/MODDUP?v=latest
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... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.
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%Warning-WIDTHTRUNC: t/t_sarif.v:13:22: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.
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: ... note: In instance 't'
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13 | wire [1:0] trunced = 5'b11111;
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| ^
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... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
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... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
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%Warning-MULTIDRIVEN: t/t_sarif.v:10:18: Signal has multiple driving blocks with different clocking: 'multidriven'
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t/t_sarif.v:15:26: ... Location of first driving block
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15 | always @(posedge clk1) multidriven <= '1;
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| ^~~~~~~~~~~
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t/t_sarif.v:16:26: ... Location of other driving block
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16 | always @(posedge clk2) multidriven <= '0;
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| ^~~~~~~~~~~
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... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
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... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
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