24 lines
508 B
Systemverilog
24 lines
508 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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virtual class uvm_object;
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endclass
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class config_obj extends uvm_object;
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function void pre_randomize();
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super.pre_randomize();
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endfunction
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function void post_randomize();
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super.post_randomize();
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endfunction
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endclass
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initial $finish;
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endmodule
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