61 lines
1.4 KiB
Systemverilog
61 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class SubClass;
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rand bit [2:0] field;
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function new();
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field = 0;
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endfunction
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endclass
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class MyClass;
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SubClass sc_inst2[int];
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function new();
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sc_inst2[1] = new;
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endfunction
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endclass
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;
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class Deep;
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MyClass sc_inst1;
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function new();
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sc_inst1 = new;
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endfunction
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endclass
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;
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class WeNeedToGoDeeper;
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Deep sc_inst;
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function new();
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sc_inst = new;
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endfunction
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endclass
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;
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module t;
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initial begin
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WeNeedToGoDeeper cl_inst[string];
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MyClass cl_inst2[int];
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cl_inst["val1"] = new;
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cl_inst2[0] = new;
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repeat (10) begin
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if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].randomize() with {
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field inside {1, 2, 3};
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} == 0) begin
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$stop;
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end
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if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin
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$stop;
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end
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if (cl_inst2[0].sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin
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$stop;
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end
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if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin
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$stop;
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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