26 lines
673 B
Systemverilog
26 lines
673 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator fargs --binary -Wno-WIDTHEXPAND
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/* verilator fargs -Wno-WIDTHTRUNC */ /* verilator fargs --trace-vcd --stats */
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module top;
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bit clk = 0;
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always #5 clk = ~clk;
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reg [3:0] cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 10'd1; // Intentional width warning
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$display("%8t %1d", $time, cyc);
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if (cyc == 3'd7) begin // Intentional width warning
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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