48 lines
1.0 KiB
Systemverilog
48 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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interface a_if #(
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parameter int a_param = 0
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) ();
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logic [a_param-1:0] x;
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function void to_if(input logic [a_param-1:0] x_in);
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x = x_in;
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endfunction
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function logic [a_param-1:0] from_if();
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return x;
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endfunction
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endinterface
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module tb ();
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genvar a;
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generate
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for (a = 1; a < 3; a++) begin : gen_a
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a_if #(.a_param(a)) a_if_a ();
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initial begin
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#1;
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a_if_a.to_if(a);
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end
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end
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endgenerate
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initial begin
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#1;
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#1;
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`checkd(gen_a[1].a_if_a.from_if(), 'h1);
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`checkd(gen_a[2].a_if_a.from_if(), 'h2);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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