66 lines
993 B
Systemverilog
66 lines
993 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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int x = 0;
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task increment_x;
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x++;
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#2;
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x++;
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endtask
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class driver;
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int m_time = 0;
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task get_and_send();
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forever begin
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#10;
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m_time += 10;
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end
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endtask
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task post_shutdown_phase();
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disable get_and_send;
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endtask
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endclass
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module t;
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driver c;
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initial begin
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fork
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increment_x();
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#1 disable increment_x;
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join
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if (x != 1) $stop;
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c = new;
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fork
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c.get_and_send;
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join_none
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if (c.m_time != 0) $stop;
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#11;
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if ($time != 12) $stop;
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if (c.m_time != 10) $stop;
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#20;
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if ($time != 32) $stop;
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if (c.m_time != 30) $stop;
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c.post_shutdown_phase;
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#20;
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if ($time != 52) $stop;
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if (c.m_time != 30) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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