51 lines
1.5 KiB
Systemverilog
51 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop;
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Test std::randomize() with associative array variables
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module t_std_randomize_assoc;
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// Associative array variables
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int assoc_int[int];
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bit [7:0] assoc_byte[string];
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initial begin
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// Test 1: std::randomize with int-keyed associative array (no constraints)
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assoc_int[0] = 0;
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assoc_int[1] = 0;
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assoc_int[2] = 0;
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`checkd(std::randomize(assoc_int), 1);
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// Test 2: std::randomize with string-keyed associative array
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assoc_byte["a"] = 0;
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assoc_byte["b"] = 0;
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assoc_byte["c"] = 0;
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`checkd(std::randomize(assoc_byte), 1);
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// Test 3: Multiple randomizations produce different values
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begin
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automatic int non_zero = 0;
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repeat (5) begin
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assoc_int[0] = 0;
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assoc_int[1] = 0;
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`checkd(std::randomize(assoc_int), 1);
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if (assoc_int[0] != 0) non_zero++;
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if (assoc_int[1] != 0) non_zero++;
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end
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// With 10 random int values, expect most non-zero
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if (non_zero < 7) `stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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