88 lines
2.0 KiB
Systemverilog
88 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Test unique constraint on explicit array element subsets (IEEE 18.5.9).
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// bit [3:0] keeps the value space small so collisions are near-certain
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// without proper constraint enforcement.
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class UniqueElemSubset;
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rand bit [3:0] arr[10];
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constraint unique_subset_con {unique {arr[2], arr[3], arr[4], arr[5], arr[6]};}
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function new();
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endfunction
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function bit check_unique();
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for (int i = 2; i <= 6; i++) begin
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for (int j = i + 1; j <= 6; j++) begin
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if (arr[i] == arr[j]) return 0;
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end
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end
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return 1;
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endfunction
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endclass
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class UniqueElemFour;
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rand bit [3:0] data[8];
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constraint unique_data_con {unique {data[1], data[2], data[3], data[4]};}
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function new();
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endfunction
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function bit check_unique();
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for (int i = 1; i <= 4; i++) begin
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for (int j = i + 1; j <= 4; j++) begin
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if (data[i] == data[j]) return 0;
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end
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end
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return 1;
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endfunction
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endclass
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class UniqueElemSingle;
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rand bit [3:0] val[4];
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constraint unique_single_con {unique {val[0]};}
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function new();
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endfunction
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endclass
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module t;
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UniqueElemSubset ues;
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UniqueElemFour uef;
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UniqueElemSingle uesgl;
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initial begin
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ues = new();
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repeat (20) begin
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`checkd(ues.randomize(), 1)
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`checkd(ues.check_unique(), 1)
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end
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uef = new();
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repeat (20) begin
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`checkd(uef.randomize(), 1)
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`checkd(uef.check_unique(), 1)
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end
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uesgl = new();
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repeat (5) begin
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`checkd(uesgl.randomize(), 1)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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