72 lines
2.0 KiB
Systemverilog
72 lines
2.0 KiB
Systemverilog
// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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// DESCRIPTION: Minimal test for sibling interface typedef resolution
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// This is the SIMPLEST case that demonstrates the t_lparam_dep_iface10 failure pattern:
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// - Two sibling cells of the same interface type with DIFFERENT parameters
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// - A module that accesses typedefs from BOTH siblings
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//
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`define stop $stop
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`define checkd(gotv,
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expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// Parameterized interface with a typedef that depends on the parameter
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interface a_if #(
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parameter int WIDTH = 8
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) ();
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localparam LP_WIDTH = WIDTH * 2;
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typedef logic [LP_WIDTH-1:0] data_t;
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data_t data;
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endinterface
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// Wrapper interface with TWO SIBLING instances of a_if with DIFFERENT widths
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interface wrapper_if #(
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parameter int WIDTH_A = 8,
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parameter int WIDTH_B = 16
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) ();
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a_if #(.WIDTH(WIDTH_A)) a_inst ();
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a_if #(.WIDTH(WIDTH_B)) b_inst ();
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// Re-export typedefs from each sibling
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typedef a_inst.data_t a_data_t;
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typedef b_inst.data_t b_data_t;
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endinterface
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// Module that accesses typedefs from BOTH siblings via interface port
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module consumer (
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wrapper_if wif
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);
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// These MUST resolve to DIFFERENT types
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typedef wif.a_inst.data_t local_a_t; // Should be 10 bits
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typedef wif.b_inst.data_t local_b_t; // Should be 20 bits
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local_a_t val_a;
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local_b_t val_b;
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initial begin
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#1;
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`checkd($bits(local_a_t), 20);
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`checkd($bits(local_b_t), 40);
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end
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endmodule
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// Top module
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module t;
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wrapper_if #(
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.WIDTH_A(10),
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.WIDTH_B(20)
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) wif ();
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consumer c (.wif(wif));
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initial begin
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#2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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