50 lines
1.2 KiB
Systemverilog
50 lines
1.2 KiB
Systemverilog
// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package a_pkg;
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typedef struct packed {int unsigned a;} cfg_t;
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endpackage
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interface depgraph_if #(
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a_pkg::cfg_t cfg = 0
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) ();
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typedef logic [cfg.a-1:0] byte_t;
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typedef struct packed {byte_t a;} pair_t;
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endinterface
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module a_mod (
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depgraph_if ifc
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);
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typedef ifc.pair_t pair_t;
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localparam p_a = $bits(pair_t);
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initial begin
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#1;
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`checkd($bits(pair_t), 8);
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`checkd(p_a, 8);
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end
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endmodule
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module t;
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localparam a_pkg::cfg_t cfg = '{a: 8};
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depgraph_if #(cfg) ifc ();
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a_mod #() a_mod_0 (.ifc(ifc));
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initial begin
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#2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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