64 lines
1.4 KiB
Systemverilog
64 lines
1.4 KiB
Systemverilog
// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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// DESCRIPTION:
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// Minimal testcase to see if unused modules with interface ports
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// still trigger ASCRANGE when interface params are defaulted.
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//
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package axi4;
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typedef struct packed {
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int IdBits;
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int AddrBits;
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int DataBits;
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int UserBits;
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} cfg_t;
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endpackage
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interface axi4_if #(
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parameter axi4::cfg_t cfg = '0
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) ();
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typedef logic [cfg.AddrBits-1:0] addr_t;
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typedef logic [cfg.DataBits-1:0] data_t;
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typedef logic [cfg.DataBits/8-1:0] strb_t;
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typedef logic [cfg.UserBits-1:0] user_t;
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typedef logic [cfg.IdBits-1:0] id_t;
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typedef struct packed {
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id_t id;
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addr_t addr;
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user_t user;
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} aw_chan_t;
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endinterface
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module dead_mod (
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axi4_if axi_io
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);
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typedef axi_io.addr_t addr_t;
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typedef axi_io.data_t data_t;
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typedef axi_io.strb_t strb_t;
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addr_t addr_d;
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data_t data_d;
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strb_t strb_d;
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endmodule
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module dead_top;
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localparam axi4::cfg_t cfg = '{IdBits: 4, AddrBits: 32, DataBits: 64, UserBits: 2};
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axi4_if #(.cfg(cfg)) axi_io ();
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dead_mod u_dead (.axi_io(axi_io));
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endmodule
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module top;
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dead_top dead_top ();
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initial begin
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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