37 lines
712 B
Systemverilog
37 lines
712 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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parameter int LEN = 32;
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class A;
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rand int x;
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rand int array[5];
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constraint a_c {
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x <= LEN;
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x >= LEN;
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foreach (array[i]) {array[i] == array[i-1];}
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}
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endclass
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class B;
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rand A a;
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endclass
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module t;
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B b;
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initial begin
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b = new;
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b.a = new;
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if (b.randomize() == 0) $stop;
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if (b.a.x != LEN) $stop;
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for (int i = 0; i < 4; i++) begin
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if (b.a.array[i] != b.a.array[i+1]) $stop;
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end
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$write("*-* All finished *-*\n");
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$finish;
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end
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endmodule
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