84 lines
1.4 KiB
Systemverilog
84 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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bit a_finished;
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bit b_finished;
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [31:0] o;
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wire si = 1'b0;
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ExampInst i ( // Outputs
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.o(o[31:0]),
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// Inputs
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.i(1'b0)
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/*AUTOINST*/);
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Prog p ( /*AUTOINST*/
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// Inputs
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.si (si));
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always @(posedge clk) begin
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if (!a_finished) $stop;
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if (!b_finished) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module InstModule (
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output logic [31:0] so,
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input si
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);
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assign so = {32{si}};
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endmodule
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program Prog (
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input si
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);
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initial a_finished = 1'b1;
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endprogram
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module ExampInst (
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o,
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i
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);
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output logic [31:0] o;
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input i;
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InstModule instName ( // Outputs
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.so(o[31:0]),
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// Inputs
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.si(i)
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/*AUTOINST*/);
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//bind InstModule Prog instProg
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// (.si(si));
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// Note is based on context of caller
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bind InstModule Prog instProg ( /*AUTOBIND*/
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.si(si)
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);
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endmodule
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// Check bind at top level
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bind InstModule Prog2 instProg2 ( /*AUTOBIND*/
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.si(si)
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);
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// Check program declared after bind
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program Prog2 (
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input si
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);
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initial b_finished = 1'b1;
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endprogram
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