36 lines
832 B
Systemverilog
36 lines
832 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog
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//
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// Assignment compatibility test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {
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int a;
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int b;
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} struct_t;
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module t;
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logic unpackedA[2];
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logic unpackedB[3];
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logic unpackedC[3][2];
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logic unpackedD[4][2];
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struct_t unpackedE[4][2];
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logic nonAggregate;
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logic assocArrayA[string];
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logic queueA[$];
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bit queueB[$];
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logic unpackedF[3] = unpackedA;
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bit unpackedG[2] = unpackedB[0:1];
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assign unpackedB = unpackedA;
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assign unpackedB = unpackedC;
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assign unpackedD = unpackedC;
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assign unpackedE = unpackedD;
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assign nonAggregate = unpackedA;
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assign unpackedA = assocArrayA;
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assign queueA = queueB;
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endmodule
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