50 lines
904 B
Systemverilog
50 lines
904 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic [3:0] enable;
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int cyc = 0;
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Test test (.*);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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`ifdef FAIL1
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enable[0] <= 1;
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`endif
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enable[1] <= 1;
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`ifdef FAIL2
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enable[2] <= 1;
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`endif
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enable[3] <= 1;
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if (cyc != 0) begin
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module Test (
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input clk,
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input [3:0] enable
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);
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assert property (@(posedge clk iff enable[0]) 0)
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else $stop;
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assert property (@(posedge clk iff enable[1]) 1);
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cover property (@(posedge clk iff enable[2]) 1) $stop;
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cover property (@(posedge clk iff enable[3]) 0) $stop;
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endmodule
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