verilator/test_regress
Yutetsu TAKATSUKASA f3b10df454
Skip merging assign statements if a variable is marked split_var to fix #3177 (#3179)
* add tests to reproduce #3177.

Any random test circuits can be added to t_split_var_4.v later because it uses CRC to check the result while
t_split_var_0.v has just barrel shifters.

* Fix #3177. Don't merge assign statements if a variable is marked split_var.
2021-10-25 20:56:59 +09:00
..
t Skip merging assign statements if a variable is marked split_var to fix #3177 (#3179) 2021-10-25 20:56:59 +09:00
.gdbinit Delay parsing of associative arrays until dtypes known. 2020-06-09 07:13:40 -04:00
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Add TRACE_THREADS to CMake (#2934) 2021-05-08 08:18:08 -04:00
Makefile Copyright year update 2021-01-01 10:29:54 -05:00
Makefile_obj Remove unused CFG_CXXFLAGS_STD_OLDEST 2021-09-26 16:01:25 -04:00
driver.pl Internal coverage: Fix some test runs having conflicting sources. 2021-10-05 20:22:29 -04:00
input.vc Internal coverage improvements 2020-09-18 21:27:36 -04:00
input.xsim.vc