31 lines
538 B
Systemverilog
31 lines
538 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top(clk, a1, a2, ready);
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input clk;
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input a1;
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input a2;
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output ready;
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wire ready_reg;
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and2_x1 and_cell (
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.a1(a1),
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.a2(a2),
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.zn(ready_reg)
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);
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assign ready = ready_reg;
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endmodule
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module and2_x1 (
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input wire a1,
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input wire a2,
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output wire zn
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);
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assign zn = (a1 & a2);
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endmodule
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