636a6b8cd2
This patch adds DfgLogic, which is a vertex that represents a whole, arbitrarily complex combinational AstAlways or AstAssignW in the DfgGraph. Implementing this requires computing the variables live at entry to the AstAlways (variables read by the block), so there is a new ControlFlowGraph data structure and a classical data-flow analysis based live variable analysis to do that at the variable level (as opposed to bit/element level). The actual CFG construction and live variable analysis is best effort, and might fail for currently unhandled constructs or data types. This can be extended later. V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices. The DfgLogic are then subsequently synthesized into primitive operations by the new V3DfgSynthesize pass, which is a combination of the old V3DfgAstToDfg conversion and new code to handle AstAlways blocks with complex flow control. V3DfgSynthesize by default will synthesize roughly the same constructs as V3DfgAstToDfg used to handle before, plus any logic that is part of a combinational cycle within the DfgGraph. This enables breaking up these cycles, for which there are extensions to V3DfgBreakCycles in this patch as well. V3DfgSynthesize will then delete all non synthesized or non synthesizable DfgLogic vertices and the rest of the Dfg pipeline is identical, with minor changes to adjust for the changed representation. Because with this change we can now eliminate many more UNOPTFLAT, DFG has been disabled in all the tests that specifically target testing the scheduling and reporting of circular combinational logic. |
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| bin | ||
| gen | ||
| guide | ||
| .gitignore | ||
| CONTRIBUTING.rst | ||
| CONTRIBUTORS | ||
| Makefile | ||
| README.rst | ||
| internals.rst | ||
| security.rst | ||
| spelling.txt | ||
| verilated.dox | ||
| xml.rst | ||
README.rst
Verilator Documentation ======================= This folder contains sources for Verilator documentation. For formatted documentation see: - `Verilator README <https://github.com/verilator/verilator>`_ - `Verilator installation and package directory structure <https://verilator.org/install>`_ - `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_ - `Subscribe to Verilator announcements <https://github.com/verilator/verilator-announce>`_ - `Verilator forum <https://verilator.org/forum>`_ - `Verilator issues <https://verilator.org/issues>`_