Krzysztof Bieganski 9edccfdffa Initial support for intra-assignment timing controls, net delays (#3427) ... This is a pre-PR to #3363. Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>		2022-05-17 19:19:44 +01:00
..
t	Initial support for intra-assignment timing controls, net delays (#3427)	2022-05-17 19:19:44 +01:00
.gdbinit	Delay parsing of associative arrays until dtypes known.	2020-06-09 07:13:40 -04:00
.gitignore	Ignore some files generated by modelsim (#2669)	2020-12-05 21:55:56 -05:00
CMakeLists.txt	Copyright year update.	2022-01-01 08:26:40 -05:00
Makefile	Copyright year update.	2022-01-01 08:26:40 -05:00
Makefile_obj	Implement 'forceable' attribute	2022-01-16 15:31:37 +00:00
driver.pl	Add assert when VerilatedContext is mis-deleted (#3121).	2022-05-15 10:51:03 -04:00
input.vc	Internal coverage improvements	2020-09-18 21:27:36 -04:00
input.xsim.vc	Add XSim support to driver.pl, bug1493.	2019-08-29 17:00:49 -04:00