83 lines
2.0 KiB
Systemverilog
83 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Alex Solomatnikov.
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// SPDX-License-Identifier: CC0-1.0
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package x_pkg;
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typedef bit unsigned [64-1:0] x_reg_data_t;
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virtual class x_reg;
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extern virtual task read(output int status, output x_reg_data_t value, input int path);
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endclass
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task x_reg::read(output int status, output x_reg_data_t value, input int path);
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endtask
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endpackage
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package s_c_env_pkg;
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import x_pkg::*;
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class r_reg_p_s_reg_n_doorbell extends x_reg;
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x_reg_data_t val;
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function new(int _val);
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val = _val;
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endfunction
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extern virtual task read(output int status, output x_reg_data_t value, input int path);
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endclass
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task r_reg_p_s_reg_n_doorbell::read(output int status, output x_reg_data_t value, input int path);
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status = 1;
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value = val;
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endtask
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class r_block_p_s_reg;
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rand r_reg_p_s_reg_n_doorbell n_doorbell;
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function new(int _val);
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n_doorbell = new(_val);
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endfunction
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endclass
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class r_top_s_reg;
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rand r_block_p_s_reg p_s[16];
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endclass
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class s_c_env;
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r_top_s_reg r_reg_model;
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endclass
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endpackage
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package s_c_sequences_pkg;
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import x_pkg::*;
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import s_c_env_pkg::*;
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class s_c_v_regs_seq;
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s_c_env m_env;
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virtual task body();
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int unsigned p, rdata;
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int status;
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if (m_env == null) m_env = new;
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if (m_env.r_reg_model == null) m_env.r_reg_model = new;
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foreach (m_env.r_reg_model.p_s[p]) begin
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if (m_env.r_reg_model.p_s[p] == null) begin
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m_env.r_reg_model.p_s[p] = new(p);
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end
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m_env.r_reg_model.p_s[p].n_doorbell.read(status, rdata, 0);
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if (status != 1) $stop;
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if (rdata != p) $stop;
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end
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endtask
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endclass
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endpackage
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module t;
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s_c_sequences_pkg::s_c_v_regs_seq seq;
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initial begin
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seq = new;
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seq.body();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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