28 lines
547 B
Systemverilog
28 lines
547 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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end
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assert property (@(posedge clk) nexttime (cyc > 0));
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always @(posedge clk) begin
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if (cyc == 20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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