38 lines
685 B
Systemverilog
38 lines
685 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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typedef enum logic [159:0] {
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E01 = 160'h1,
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ELARGE = 160'h1234_4567_abcd_1234_4567_abcd
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} my_t;
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my_t e;
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int cyc;
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// Check runtime
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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// Setup
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e <= E01;
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end
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else if (cyc == 1) begin
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$display(e.name);
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e <= ELARGE;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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