45 lines
1.1 KiB
Systemverilog
45 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA.
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module t();
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/*stray pragma */ /*verilator split_var*/
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// The following variables can not be splitted. will see warnings.
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real should_show_warning0; /*verilator split_var*/
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string should_show_warning1[0:2]; /*verilator split_var*/
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wire should_show_warning2; /*verilator split_var*/
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logic [3:0] addr;
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logic [7:0] rd_data0, rd_data1, rd_data2;
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sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
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sub1 i_sub1(.addr(addr), .rd_data(rd_data2));
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initial begin
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addr = 0;
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addr = 1;
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$finish;
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end
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endmodule
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module sub0(input [3:0]addr, output logic [7:0] rd_data);
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logic [7:0] cannot_split[0:15]; /*verilator split_var*/
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always_comb
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rd_data = cannot_split[addr];
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endmodule
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module sub1(input [3:0]addr, output logic [7:0] rd_data);
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logic [15:0] [7:0] cannot_split; /*verilator split_var*/
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always_comb
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rd_data = cannot_split[addr];
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endmodule
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