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https://github.com/verilator/verilator.git
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Geza Lore
976ec63531
Arrays of module instances are now expanded into their element cells during elaboration in V3Param, instead of after V3Width in V3Inst::dearrayAll. Element cells are named as before (name__BRA__i__KET__...), are ordered from the left index to the right index, and hierarchical references to them resolve in linkDotParamed. Arrays of interface instances are still expanded by V3Inst. They will move in a follow up patch. Algorithmically: - V3Praram replaces an arrayed AstCell, with a scalar Cell for each element. linkDotParamed can resolve against these as normal. - V3Width then fixes up the AstPins of each expanded Cell according to the LRM rules. Either leaving the alone to connect to all instances, or inserting ArraySel/Sel to connect the relevant part to the relevant instance. Partial #2675
17 lines
512 B
Python
Executable File
17 lines
512 B
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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