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30 lines
662 B
Systemverilog
30 lines
662 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk,
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input bit [3:0] sel,
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input bit [3:0] a,
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input bit c,
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output bit dout
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);
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localparam logic DC = 1'b?;
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always_ff @(posedge clk) begin
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unique casez (sel)
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4'b0000: dout <= a[0];
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4'b001?: dout <= a[1];
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{1'b0, 1'b1, 1'b?, 1'b?} : dout <= a[2];
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{1'b1, 1'b?, 1'b?, DC} : dout <= a[3];
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default: dout <= '0;
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endcase
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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