234 lines
11 KiB
XML
234 lines
11 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2023"/>
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<file id="b" filename="<command-line>" language="1800-2023"/>
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<file id="c" filename="input.vc" language="1800-2023"/>
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<file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_constraint_xml.v" language="1800-2023"/>
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</module_files>
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<cells>
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<cell loc="d,65,8,65,9" name="t" submodname="t" hier="t"/>
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</cells>
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<netlist>
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<module loc="d,65,8,65,9" name="t" origName="t">
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<var loc="d,67,11,67,12" name="p" dtype_id="1" vartype="Packet" origName="p"/>
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<initial loc="d,69,4,69,11">
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<begin loc="d,69,12,69,17">
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<display loc="d,71,7,71,13" displaytype="$write">
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<sformatf loc="d,71,7,71,13" name="*-* All Finished *-* " dtype_id="2"/>
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</display>
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<finish loc="d,72,7,72,14"/>
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</begin>
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</initial>
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</module>
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<package loc="a,0,0,0,0" name="$unit" origName="__024unit">
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<class loc="d,7,1,7,6" name="Packet" origName="Packet">
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<var loc="d,8,13,8,19" name="header" dtype_id="3" vartype="int" origName="header"/>
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<var loc="d,9,13,9,19" name="length" dtype_id="3" vartype="int" origName="length"/>
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<var loc="d,10,13,10,22" name="sublength" dtype_id="3" vartype="int" origName="sublength"/>
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<var loc="d,11,13,11,17" name="if_4" dtype_id="4" vartype="bit" origName="if_4"/>
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<var loc="d,12,13,12,20" name="iff_5_6" dtype_id="4" vartype="bit" origName="iff_5_6"/>
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<var loc="d,13,13,13,24" name="if_state_ok" dtype_id="4" vartype="bit" origName="if_state_ok"/>
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<var loc="d,15,13,15,18" name="array" dtype_id="5" vartype="" origName="array"/>
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<var loc="d,17,11,17,16" name="state" dtype_id="2" vartype="string" origName="state"/>
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<constraint loc="d,19,15,19,20" name="empty"/>
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<constraint loc="d,21,15,21,19" name="size">
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<constraintexpr loc="d,22,18,22,20">
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<and loc="d,22,18,22,20" dtype_id="6">
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<lts loc="d,22,14,22,15" dtype_id="6">
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<const loc="d,22,16,22,17" name="32'sh0" dtype_id="7"/>
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<varref loc="d,22,7,22,13" name="header" dtype_id="3"/>
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</lts>
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<gtes loc="d,22,28,22,30" dtype_id="6">
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<const loc="d,22,31,22,32" name="32'sh7" dtype_id="7"/>
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<varref loc="d,22,21,22,27" name="header" dtype_id="3"/>
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</gtes>
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</and>
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</constraintexpr>
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<constraintexpr loc="d,23,14,23,16">
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<gtes loc="d,23,14,23,16" dtype_id="6">
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<const loc="d,23,17,23,19" name="32'shf" dtype_id="7"/>
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<varref loc="d,23,7,23,13" name="length" dtype_id="3"/>
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</gtes>
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</constraintexpr>
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<constraintexpr loc="d,24,14,24,16">
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<gtes loc="d,24,14,24,16" dtype_id="6">
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<varref loc="d,24,7,24,13" name="length" dtype_id="3"/>
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<varref loc="d,24,17,24,23" name="header" dtype_id="3"/>
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</gtes>
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</constraintexpr>
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<constraintexpr loc="d,25,7,25,13">
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<varref loc="d,25,7,25,13" name="length" dtype_id="3"/>
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</constraintexpr>
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</constraint>
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<constraint loc="d,28,15,28,18" name="ifs">
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<if loc="d,29,7,29,9">
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<lts loc="d,29,18,29,19" dtype_id="6">
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<const loc="d,29,20,29,21" name="32'sh4" dtype_id="7"/>
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<varref loc="d,29,11,29,17" name="header" dtype_id="3"/>
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</lts>
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<begin>
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<constraintexpr loc="d,30,15,30,17">
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<varref loc="d,30,10,30,14" name="if_4" dtype_id="6"/>
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</constraintexpr>
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</begin>
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</if>
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<if loc="d,32,7,32,9">
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<or loc="d,32,23,32,25" dtype_id="6">
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<eq loc="d,32,18,32,20" dtype_id="6">
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<const loc="d,32,21,32,22" name="32'sh5" dtype_id="7"/>
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<varref loc="d,32,11,32,17" name="header" dtype_id="3"/>
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</eq>
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<eq loc="d,32,33,32,35" dtype_id="6">
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<const loc="d,32,36,32,37" name="32'sh6" dtype_id="7"/>
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<varref loc="d,32,26,32,32" name="header" dtype_id="3"/>
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</eq>
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</or>
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<begin>
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<constraintexpr loc="d,33,18,33,20">
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<varref loc="d,33,10,33,17" name="iff_5_6" dtype_id="6"/>
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</constraintexpr>
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</begin>
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<begin>
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<constraintexpr loc="d,35,18,35,20">
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<not loc="d,35,18,35,20" dtype_id="4">
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<varref loc="d,35,10,35,17" name="iff_5_6" dtype_id="4"/>
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</not>
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</constraintexpr>
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</begin>
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</if>
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</constraint>
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<constraint loc="d,39,15,39,23" name="arr_uniq">
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<constraintforeach loc="d,40,7,40,14">
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<selloopvars loc="d,40,21,40,22">
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<varref loc="d,40,16,40,21" name="array" dtype_id="5"/>
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<var loc="d,40,22,40,23" name="i" dtype_id="8" vartype="integer" origName="i"/>
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</selloopvars>
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<constraintexpr loc="d,41,19,41,25">
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<or loc="d,41,19,41,25" dtype_id="6">
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<or loc="d,41,19,41,25" dtype_id="6">
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<eqwild loc="d,41,27,41,28" dtype_id="6">
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<arraysel loc="d,41,15,41,16" dtype_id="3">
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<varref loc="d,41,10,41,15" name="array" dtype_id="5"/>
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<sel loc="d,41,16,41,17" dtype_id="9">
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<varref loc="d,41,16,41,17" name="i" dtype_id="8"/>
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<const loc="d,41,16,41,17" name="32'h0" dtype_id="10"/>
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<const loc="d,41,16,41,17" name="32'h1" dtype_id="10"/>
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</sel>
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</arraysel>
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<const loc="d,41,27,41,28" name="32'sh2" dtype_id="7"/>
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</eqwild>
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<eqwild loc="d,41,30,41,31" dtype_id="6">
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<arraysel loc="d,41,15,41,16" dtype_id="3">
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<varref loc="d,41,10,41,15" name="array" dtype_id="5"/>
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<sel loc="d,41,16,41,17" dtype_id="9">
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<varref loc="d,41,16,41,17" name="i" dtype_id="8"/>
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<const loc="d,41,16,41,17" name="32'h0" dtype_id="10"/>
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<const loc="d,41,16,41,17" name="32'h1" dtype_id="10"/>
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</sel>
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</arraysel>
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<const loc="d,41,30,41,31" name="32'sh4" dtype_id="7"/>
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</eqwild>
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</or>
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<eqwild loc="d,41,33,41,34" dtype_id="6">
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<arraysel loc="d,41,15,41,16" dtype_id="3">
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<varref loc="d,41,10,41,15" name="array" dtype_id="5"/>
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<sel loc="d,41,16,41,17" dtype_id="9">
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<varref loc="d,41,16,41,17" name="i" dtype_id="8"/>
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<const loc="d,41,16,41,17" name="32'h0" dtype_id="10"/>
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<const loc="d,41,16,41,17" name="32'h1" dtype_id="10"/>
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</sel>
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</arraysel>
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<const loc="d,41,33,41,34" name="32'sh6" dtype_id="7"/>
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</eqwild>
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</or>
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</constraintexpr>
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</constraintforeach>
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<constraintunique loc="d,43,7,43,13">
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<arraysel loc="d,43,21,43,22" dtype_id="3">
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<varref loc="d,43,16,43,21" name="array" dtype_id="5"/>
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<const loc="d,43,22,43,23" name="1'h0" dtype_id="9"/>
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</arraysel>
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<arraysel loc="d,43,31,43,32" dtype_id="3">
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<varref loc="d,43,26,43,31" name="array" dtype_id="5"/>
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<const loc="d,43,32,43,33" name="1'h1" dtype_id="9"/>
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</arraysel>
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</constraintunique>
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</constraint>
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<constraint loc="d,46,15,46,20" name="order">
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<constraintbefore loc="d,46,23,46,28">
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<varref loc="d,46,29,46,35" name="length" dtype_id="3"/>
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<varref loc="d,46,43,46,49" name="header" dtype_id="3"/>
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</constraintbefore>
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</constraint>
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<constraint loc="d,48,15,48,18" name="dis">
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<constraintexpr loc="d,49,7,49,11">
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<varref loc="d,49,12,49,21" name="sublength" dtype_id="3"/>
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</constraintexpr>
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<constraintexpr loc="d,50,7,50,14">
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<varref loc="d,50,20,50,29" name="sublength" dtype_id="3"/>
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</constraintexpr>
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<constraintexpr loc="d,51,17,51,19">
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<ltes loc="d,51,17,51,19" dtype_id="6">
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<varref loc="d,51,7,51,16" name="sublength" dtype_id="3"/>
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<varref loc="d,51,20,51,26" name="length" dtype_id="3"/>
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</ltes>
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</constraintexpr>
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</constraint>
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<constraint loc="d,54,15,54,19" name="meth">
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<if loc="d,55,7,55,9">
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<funcref loc="d,55,11,55,24" name="strings_equal" dtype_id="4">
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<arg loc="d,55,25,55,30">
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<varref loc="d,55,25,55,30" name="state" dtype_id="2"/>
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</arg>
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<arg loc="d,55,32,55,36">
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<const loc="d,55,32,55,36" name=""ok"" dtype_id="2"/>
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</arg>
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</funcref>
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<begin>
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<constraintexpr loc="d,56,22,56,24">
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<varref loc="d,56,10,56,21" name="if_state_ok" dtype_id="6"/>
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</constraintexpr>
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</begin>
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</if>
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</constraint>
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<func loc="d,59,17,59,30" name="strings_equal" dtype_id="4">
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<var loc="d,59,17,59,30" name="strings_equal" dtype_id="4" dir="output" vartype="bit" origName="strings_equal"/>
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<var loc="d,59,38,59,39" name="a" dtype_id="2" dir="input" vartype="string" origName="a"/>
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<var loc="d,59,48,59,49" name="b" dtype_id="2" dir="input" vartype="string" origName="b"/>
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<assign loc="d,60,7,60,13" dtype_id="4">
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<eqn loc="d,60,16,60,18" dtype_id="6">
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<varref loc="d,60,14,60,15" name="a" dtype_id="2"/>
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<varref loc="d,60,19,60,20" name="b" dtype_id="2"/>
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</eqn>
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<varref loc="d,60,7,60,13" name="strings_equal" dtype_id="4"/>
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</assign>
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</func>
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<func loc="d,7,1,7,6" name="new" dtype_id="11"/>
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</class>
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</package>
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<typetable loc="a,0,0,0,0">
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<basicdtype loc="d,22,14,22,15" id="6" name="logic"/>
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<basicdtype loc="d,25,21,25,22" id="10" name="logic" left="31" right="0"/>
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<basicdtype loc="d,71,7,71,13" id="2" name="string"/>
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<basicdtype loc="d,40,22,40,23" id="8" name="integer" left="31" right="0" signed="true"/>
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<basicdtype loc="d,8,9,8,12" id="3" name="int" left="31" right="0" signed="true"/>
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<basicdtype loc="d,11,9,11,12" id="4" name="bit"/>
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<unpackarraydtype loc="d,15,18,15,19" id="5" sub_dtype_id="3">
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<range loc="d,15,18,15,19">
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<const loc="d,15,19,15,20" name="32'h0" dtype_id="10"/>
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<const loc="d,15,19,15,20" name="32'h1" dtype_id="10"/>
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</range>
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</unpackarraydtype>
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<basicdtype loc="d,32,18,32,20" id="9" name="logic" signed="true"/>
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<voiddtype loc="d,7,1,7,6" id="11"/>
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<classrefdtype loc="d,67,4,67,10" id="1" name="Packet"/>
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<basicdtype loc="d,22,16,22,17" id="7" name="logic" left="31" right="0" signed="true"/>
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</typetable>
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</netlist>
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</verilator_xml>
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