Yutetsu TAKATSUKASA b08c694cd6 Fix wrong bit op tree optimization (#3185) ... * Add a test to reproduce bug3182. Run the same HDL with -Oo to confirm the result is same. * Hopefully fix #3182. The result can be 0 only when polarity is true (no AstNot is found during traversal).		2021-11-06 12:31:50 +09:00
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t	Fix wrong bit op tree optimization (#3185)	2021-11-06 12:31:50 +09:00
.gdbinit	Delay parsing of associative arrays until dtypes known.	2020-06-09 07:13:40 -04:00
.gitignore	Ignore some files generated by modelsim (#2669)	2020-12-05 21:55:56 -05:00
CMakeLists.txt	Add TRACE_THREADS to CMake (#2934)	2021-05-08 08:18:08 -04:00
Makefile	Copyright year update	2021-01-01 10:29:54 -05:00
Makefile_obj	Remove unused CFG_CXXFLAGS_STD_OLDEST	2021-09-26 16:01:25 -04:00
driver.pl	Internal coverage: Fix some test runs having conflicting sources.	2021-10-05 20:22:29 -04:00
input.vc	Internal coverage improvements	2020-09-18 21:27:36 -04:00
input.xsim.vc	Add XSim support to driver.pl, bug1493.	2019-08-29 17:00:49 -04:00