verilator/test_regress
Geza Lore d330100542 Create implicit nets for inputs of gate primitives.
Prior to this we failed to create implicit nets for inputs of gate
primitives, which is required by the standard (IEEE 1800-2017 6.10).
Note: outputs were covered due to being modeled as the LHS of
assignments, which do create implicit nets.
2023-10-21 22:45:26 +01:00
..
t Create implicit nets for inputs of gate primitives. 2023-10-21 22:45:26 +01:00
.gdbinit Revert .gdbinit modified by accident. (#4330) 2023-06-30 16:57:31 -04:00
.gitignore
CMakeLists.txt Fix cmake 3.12+ warnings on MSWIN. 2023-02-03 17:16:39 -05:00
Makefile Copyright year update 2023-01-01 10:18:39 -05:00
Makefile_obj Make VL_LOCK_SPINS configurable 2023-10-21 18:05:53 +01:00
driver.pl Fix clang error (#4462) 2023-09-26 21:07:43 -04:00
input.vc
input.xsim.vc