verilator/test_regress
Geza Lore 4f36e3e6c9
Fix incorrect condition in varNotReferenced (#2873)
The intention was to not merge impure assignments, but the actual
predicate failed if the assignment was indeed pure.

This fix gains 1.5% speed on SweRV EH1.
2021-04-03 12:57:06 -04:00
..
t Fix incorrect condition in varNotReferenced (#2873) 2021-04-03 12:57:06 -04:00
.gdbinit Delay parsing of associative arrays until dtypes known. 2020-06-09 07:13:40 -04:00
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Copyright year update 2021-01-01 10:29:54 -05:00
Makefile Copyright year update 2021-01-01 10:29:54 -05:00
Makefile_obj Copyright year update 2021-01-01 10:29:54 -05:00
driver.pl Tests: Honor make_top_shell=>0 (#2847). 2021-04-01 08:52:48 -04:00
input.vc Internal coverage improvements 2020-09-18 21:27:36 -04:00
input.xsim.vc Add XSim support to driver.pl, bug1493. 2019-08-29 17:00:49 -04:00