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8868d459a2
* Fix broken support of unassigned virtual interfaces Unassigned virtual interface support added by #6245 is broken - PR marks dead module as alive - we can't do that as once a module is dead it needs to remain dead because earlier steps (e.g. port resolution) have already been skipped. This commit handles unassigned virtual interfaces at the beginning of first pass of LinkDot (so it is never marked as dead, and no linking steps are getting skipped). Fixes #6253. * Apply suggestions from code review Co-authored-by: Wilson Snyder <[email protected]> * Apply 'make format' * Revert add of redundant iterateChildren() call * Add original test case --------- Co-authored-by: Wilson Snyder <[email protected]> Co-authored-by: github action <[email protected]>
17 lines
502 B
Python
Executable File
17 lines
502 B
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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