32 lines
560 B
Systemverilog
32 lines
560 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int cnt = 0;
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task automatic myTask;
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fork
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begin
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bit x;
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if (!x) begin
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cnt++;
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end
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if (!$onehot(x)) begin
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cnt++;
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end
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end
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join_none
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endtask
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initial begin
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myTask();
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#1;
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if (cnt != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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