250 lines
6.1 KiB
Systemverilog
250 lines
6.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`ifdef USE_VPI_NOT_DPI
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//We call it via $c so we can verify DPI isn't required - see bug572
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`else
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import "DPI-C" context function int mon_check();
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`endif
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module t
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/* verilator public_flat_on */
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#(
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parameter int visibleParam1 = 0,
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/* verilator public_off */
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parameter int invisibleParam1 = 1,
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/* verilator public_on */
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parameter int visibleParam2 = 2
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/* verilator public_off */
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)
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(/*AUTOARG*/
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// Outputs
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x,
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// Inputs
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clk, a
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);
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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input clk;
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input [7:0] a /* verilator public_flat_rw */;
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output reg [7:0] x /* verilator public_flat_rw */;
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/*verilator public_flat_rw_on @(posedge clk)*/
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reg onebit;
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reg [2:1] twoone;
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reg [2:1] fourthreetwoone[4:3];
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reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND;
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// verilator lint_off ASCRANGE
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reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/;
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reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */;
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/*verilator public_off*/
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reg invisible1;
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// verilator lint_on ASCRANGE
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/*verilator public_flat_on*/
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reg [31:0] count;
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reg [31:0] half_count = 0;
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/*verilator public_off*/
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/*verilator public_flat_rw_on*/
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reg [31:0] delayed;
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reg [31:0] delayed_mem [16];
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reg [7:0] \escaped_with_brackets[3] ;
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reg [7:0] mem_2d[3:0][7:0]; // Descending indices
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// verilator lint_off ASCRANGE
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reg [0:95] mem_3d[0:1][1:0][0:1]; // Mixed: asc, desc, asc
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// Signal with multiple packed dimensions
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reg [0:15][0:3][7:0] multi_packed[2:0];
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reg [8:-7] [3:-4] negative_multi_packed[0:-2];
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// verilator lint_on ASCRANGE
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reg unpacked_only[7:0];
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/*verilator public_off*/
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reg invisible2;
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/*verilator public_flat_rw_on @(posedge clk)*/
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reg [7:0] text_byte;
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reg [15:0] text_half;
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reg [31:0] text_word;
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reg [63:0] text_long;
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reg [511:0] text;
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reg [2047:0] too_big;
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/*verilator public_off*/
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integer status;
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/*verilator public_flat_rw_on*/
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bit bit1;
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integer integer1;
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byte byte1;
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shortint short1;
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int int1;
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longint long1;
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real real1;
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string str1;
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localparam int nullptr = 123;
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logic [31:0] some_mem [4] = {0, 0, 0, 432};
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/*verilator public_off*/
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generate
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for (genvar i = 0; i < 1; i++) begin : gen
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wire [7:0] gen_sig /*verilator public_flat_rw*/ = 8'hAB;
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end
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endgenerate
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sub sub();
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// Test loop
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initial begin
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count = 0;
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delayed = 0;
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onebit = 1'b0;
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fourthreetwoone[3] = 0; // stop icarus optimizing away
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text_byte = "B";
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text_half = "Hf";
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text_word = "Word";
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text_long = "Long64b";
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text = "Verilog Test module";
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too_big = "some text";
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bit1 = 1;
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integer1 = 123;
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byte1 = 123;
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short1 = 123;
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int1 = 123;
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long1 = 123;
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real1 = 1.0;
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str1 = "hello";
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\escaped_with_brackets[3] = 8'h5a;
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rev = 12'habc;
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for (int i = 0; i < 4; i++) begin
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for (int j = 0; j < 8; j++) begin
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mem_2d[i][j] = 8'(((i * 8) + j));
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end
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end
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for (int i = 0; i < 2; i++) begin
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for (int j = 0; j < 2; j++) begin
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for (int k = 0; k < 2; k++) begin
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mem_3d[i][j][k] = 96'(((i * 4) + (j * 2) + k));
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end
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end
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end
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for (int i = 0; i < 3; i++) begin
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for (int j = 0; j < 16; j++) begin
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for (int k = 0; k < 4; k++) begin
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multi_packed[i][j][k] = 8'(((i * 64) + (j * 4) + k));
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end
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end
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end
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for (int i = -2; i <= 0; i++) begin
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for (int j = -7; j <= 8; j++) begin
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negative_multi_packed[i][j] = 8'(((i + 2) * 4) + (j + 2));
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end
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end
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`endif
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`ifdef IVERILOG
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status = $mon_check();
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`endif
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`ifndef USE_VPI_NOT_DPI
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status = mon_check();
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`endif
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if (status!=0) begin
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$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("%%Info: Checking results\n");
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if (onebit != 1'b1) $stop;
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if (quads[2] != 62'h12819213_abd31a1c) $stop;
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if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
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if (text_byte != "A") $stop;
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if (text_half != "T2") $stop;
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if (text_word != "Tree") $stop;
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if (text_long != "44Four44") $stop;
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if (text != "lorem ipsum") $stop;
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if (str1 != "something a lot longer than hello") $stop;
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if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop;
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end
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always @(posedge clk) begin
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count <= count + 2;
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if (count[1])
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half_count <= half_count + 2;
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if (count == 1000) begin
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if (delayed != 123) $stop;
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if (delayed_mem[7] != 456) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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genvar i;
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generate
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for (i=1; i<=6; i=i+1) begin : arr
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arr #(.LENGTH(i)) arr();
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end
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endgenerate
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genvar k;
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generate
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for (k=1; k<=6; k=k+1) begin : subs
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sub subsub();
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end
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endgenerate
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arr #(.LENGTH(8)) \escaped.inst[0] ();
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endmodule : t
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module sub;
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reg subsig1 /*verilator public_flat_rw*/;
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reg subsig2 /*verilator public_flat_rd*/;
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`ifdef IVERILOG
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// stop icarus optimizing signals away
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wire redundant = subsig1 | subsig2;
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`endif
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endmodule : sub
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module arr;
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parameter LENGTH = 1;
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/*verilator public_flat_rw_on*/
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reg [LENGTH-1:0] sig;
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reg [LENGTH-1:0] rfr;
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reg [LENGTH-1:0] \escaped_sig[1] /*verilator public_flat_rw*/;
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reg check;
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reg verbose;
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/*verilator public_off*/
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initial begin
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sig = {LENGTH{1'b0}};
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rfr = {LENGTH{1'b0}};
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end
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always @(posedge check) begin
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if (verbose) $display("%m : %x %x", sig, rfr);
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if (check && sig != rfr) $stop;
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check <= 0;
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end
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endmodule : arr
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