18 lines
326 B
Systemverilog
18 lines
326 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 George Polack
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// SPDX-License-Identifier: CC0-1.0
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module t (
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// Outputs
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o_z,
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// Inputs
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i_a
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);
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input real i_a;
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output real o_z;
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assign o_z = i_a;
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endmodule
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