30 lines
651 B
Systemverilog
30 lines
651 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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parameter [31:0] P2 = 2, P3 = 3;
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integer i2 = 2, i3 = 3;
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reg [31:0] r2 = 2, r3 = 3;
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wire [31:0] w2 = 2, w3 = 3;
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always @(posedge clk) begin
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if (P2 !== 2) $stop;
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if (P3 !== 3) $stop;
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if (i2 !== 2) $stop;
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if (i3 !== 3) $stop;
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if (r2 !== 2) $stop;
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if (r3 !== 3) $stop;
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if (w2 !== 2) $stop;
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if (w3 !== 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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