34 lines
660 B
Systemverilog
34 lines
660 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer varfirst;
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sub varfirst (); // Error: Cell hits var
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task varfirst;
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begin
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end
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endtask // Error: Task hits var
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sub cellfirst ();
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integer cellfirst; // Error: Var hits cell
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task cellfirst;
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begin
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end
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endtask // Error: Task hits cell
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task taskfirst;
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begin
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end
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endtask
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integer taskfirst; // Error: Var hits task
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sub taskfirst (); // Error: Cell hits task
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endmodule
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module sub;
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endmodule
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