70 lines
1.2 KiB
Systemverilog
70 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Mike Thyer
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg a, b, sel, z;
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udp_mux2(
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z, a, b, sel
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);
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int cycle = 0;
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always @(posedge clk) begin
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cycle <= cycle + 1;
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if (cycle == 0) begin
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a = 0;
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b = 1;
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sel = 0;
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end
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else if (cycle == 1) begin
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a = 1;
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b = 1;
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sel = 0;
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if (z != 0) $stop;
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end
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else if (cycle == 2) begin
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a = 0;
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b = 1;
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sel = 0;
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if (z != 1) $stop;
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end
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else if (cycle == 3) begin
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a = 1;
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b = 0;
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sel = 0;
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if (z != 0) $stop;
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end
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else if (cycle == 4) begin
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if (z != 1) $stop;
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end
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else if (cycle >= 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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primitive udp_mux2(z, a, b, sel);
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output z;
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input a, b, sel;
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table
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//a b s o
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? 1 1 : 1;
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? 0 1 : 0;
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1 ? 0 : 1;
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0 ? 0 : 0;
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1 1 x : 1;
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// Next blank line is intentional for parser
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// Next \ at EOL is intentional for parser
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0 0 x \
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: 0 ;
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endtable
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endprimitive
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