150 lines
3.6 KiB
Systemverilog
150 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2004 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// Check empty blocks
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task EmptyFor;
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/* verilator public */
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integer i;
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begin
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for (i = 0; i < 2; i = i + 1) begin
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end
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end
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endtask
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// Check look unroller
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reg signed signed_tests_only = 1'sb1;
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integer total;
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integer i;
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reg [31:0] iu;
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reg [31:0] dly_to_ensure_was_unrolled[1:0];
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reg [2:0] i3;
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integer cyc;
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initial cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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case (cyc)
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1: begin
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// >= signed
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total = 0;
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for (i = 5; i >= 0; i = i - 1) begin
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total = total - i - 1;
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dly_to_ensure_was_unrolled[i] <= i;
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end
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if (total != -21) $stop;
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end
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2: begin
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// > signed
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total = 0;
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for (i = 5; i > 0; i = i - 1) begin
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total = total - i - 1;
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dly_to_ensure_was_unrolled[i] <= i;
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end
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if (total != -20) $stop;
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end
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3: begin
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// < signed
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total = 0;
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for (i = 1; i < 5; i = i + 1) begin
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total = total - i - 1;
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dly_to_ensure_was_unrolled[i] <= i;
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end
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if (total != -14) $stop;
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end
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4: begin
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// <= signed
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total = 0;
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for (i = 1; i <= 5; i = i + 1) begin
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total = total - i - 1;
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dly_to_ensure_was_unrolled[i] <= i;
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end
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if (total != -20) $stop;
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end
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// UNSIGNED
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5: begin
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// >= unsigned
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total = 0;
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for (iu = 5; iu >= 1; iu = iu - 1) begin
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total = total - iu - 1;
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dly_to_ensure_was_unrolled[iu] <= iu;
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end
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if (total != -20) $stop;
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end
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6: begin
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// > unsigned
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total = 0;
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for (iu = 5; iu > 1; iu = iu - 1) begin
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total = total - iu - 1;
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dly_to_ensure_was_unrolled[iu] <= iu;
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end
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if (total != -18) $stop;
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end
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7: begin
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// < unsigned
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total = 0;
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for (iu = 1; iu < 5; iu = iu + 1) begin
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total = total - iu - 1;
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dly_to_ensure_was_unrolled[iu] <= iu;
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end
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if (total != -14) $stop;
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end
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8: begin
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// <= unsigned
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total = 0;
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for (iu = 1; iu <= 5; iu = iu + 1) begin
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total = total - iu - 1;
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dly_to_ensure_was_unrolled[iu] <= iu;
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end
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if (total != -20) $stop;
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end
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//===
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9: begin
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// mostly cover a small index
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total = 0;
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for (i3 = 3'd0; i3 < 3'd7; i3 = i3 + 3'd1) begin
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total = total - {29'd0, i3} - 1;
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dly_to_ensure_was_unrolled[i3[0]] <= 0;
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end
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if (total != -28) $stop;
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end
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//===
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10: begin
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// mostly cover a small index
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total = 0;
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for (i3 = 0; i3 < 3'd7; i3 = i3 + 3'd1) begin
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total = total - {29'd0, i3} - 1;
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dly_to_ensure_was_unrolled[i3[0]] <= 0;
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end
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if (total != -28) $stop;
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end
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//===
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11: begin
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// width violation on <, causes extend
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total = 0;
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for (i3 = 3'd0; i3 < 7; i3 = i3 + 1) begin
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total = total - {29'd0, i3} - 1;
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dly_to_ensure_was_unrolled[i3[0]] <= 0;
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end
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if (total != -28) $stop;
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end
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//===
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// width violation on <, causes extend signed
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// Unsupported as yet
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//===
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19: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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default: ;
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endcase
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end
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endmodule
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